cycle interrupt

英 [ˈsaɪkl ˌɪntəˈrʌpt]

美 [ˈsaɪkl ˌɪntəˈrʌpt]

网络周期性中断; 周期中断

But the traditional software time will arise the accumulative error because the time cycle is not considered perfectly, because of the interrupt response time is not confirmed, the error arose by the timer interrupt method is not rooted.
但是传统的软件定时方式由于时钟周期考虑不全容易引起累积误差，而采用定时器中断方式定时由于中断响应周期不确定性而产生的误差更具有非固定性的特点。
This paper introduces the method of execution-cycle multiplexing and the designs of interrupt flag signals using register model in interrupt module architecture. Some control signals are illustrated with Verilog HDL design in detail.
文章介绍了一种采用中断执行周期复用、寄存器模型设计中断标识信号的中断电路实现方法，并给出了关键控制信号的Veriloghdl程序实现。
The internal modules of slave FPGA equipment mainly include: the VME bus cycle, the interrupt request module, timer module and so on.
从设备FPGA内部模块主要包括本地总线周期，VME总线周期，中断请求器模块，以及定时器模块等。
The interrupt cycle of the general I/ O card is at ns level, and the system realizes the control of the galvanometric scanner through interrupt response.
中断I/O卡的中断周期在ns级，通过系统实时响应中断请求来实现对振镜式激光扫描系统的实时控制。